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Samsung mass produces industry's first 3D NAND flash chips

Lucas Mearian | Aug. 6, 2013
The 3D flash technology lays a foundation for next generation 1Tbit chips.

But 3D NAND also has its limits, and it's expected to reach those by the end of this decade, according to Wong.

"For 3D NAND, like a skyscraper, once you reach a certain level it becomes too expensive. There's no cost benefit after a while. You can only build a skyscraper so high," he said.

Currently, other technologies, such as resistive random-access memory (RRAM), Racetrack Memory, Graphene Memory and Phase-Change Memory are being viewed as future contenders to NAND flash. In 3D NAND flash, each layer of substrate requires a dielectric or electrical insulator. Currently, the dielectric material is 50nm. Making it thicker could slow the flow of electrons causing the memory's performance to falter. Making it too thin could cause electrical loss, just like in planar flash, thereby introducing data errors.

"It's very difficult to shrink dialetrics, so there's a tradeoff with reliability," Wong said. "It's a balance between all the materials in the device. You need to find right balance between performance and reliability."

Samsung said it has spent nearly 10 years of research and development on 3D Vertical NAND, and it now has more than 300 patent-pending 3D memory technologies worldwide. The company said its 3D technology has set the foundation for more advanced products including one terabit (Tb) NAND flash chips.

"The new 3D V-NAND flash technology is the result of our employees' years of efforts to push beyond conventional ways of thinking and pursue much more innovative approaches in overcoming limitations in the design of memory semiconductor technology," said Jeong-Hyuk Choi, senior vice president, flash product & technology, Samsung Electronics. "Following the world's first mass production of 3D Vertical NAND, we will continue to introduce 3D V-NAND products with improved performance and higher density, which will contribute to further growth of the global memory industry."

For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and cost.

Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and manufacturing processes through which vertical stacking of planar cell layers for a new 3D structure has been successfully developed.

To do this, Samsung revamped its CTF architecture, which was first developed in 2006. Samsung's CTF-based NAND flash architecture temporarily places an electric charge in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighboring cells.


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