Samsung Electronics Monday said it is now mass producing chips that stack layers of data-storing silicon like a microscopic skyscraper, creating what will undeniably be the NAND flash technology for the immediate future.
The move lets Samsung boast an industry first, three-dimensional (3D) Vertical NAND (V-NAND) flash memory that breaks through current 2D or planar NAND scaling limits.
Samsung's new V-NAND 3D flash memory wafer
Once used to create embedded memory and solid-state drives, Samsung's V-NAND will boast capacities ranging from 128GB to 1TB, "depending on customer demand."
"In the future, they could go considerably higher than that," said Steve Weinger, director of NAND Marketing for Samsung Semiconductor.
The most-dense process for creating cells to store data on current planar NAND is between 10 nanometer (nm) to 19nm in size. To give some idea of how small that is, a nanometer is one-billionth of a meter — a human hair is 3,000 times thicker than NAND flash made with 25nm process technology. There are 25 million nanometers in an inch.
Samsung's 3D NAND technology achieves gains in both area ratio and performance, the company said. The new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid-state drives (SSDs).
Samsung's new V-NAND offers a 128 bit density in a single chip, the same as that now produced by planar NAND technology companies such as Intel and Micron.
Samsung's V-NAND, however, uses cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying the latter technologies, Samsung's 3D V-NAND can provide over twice the scaling of 20nm-class planar NAND flash.
One of the most important technological achievements of the new Samsung V-NAND announcement is that the proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom.
It's not yet known what the limits will be for stacking cell layers in 3D NAND memory, analysts said.
"Right now it's 24. The next generation, it may be 32. Then that'll increase," said Gregory Wong, founder and principal analyst at research firm Forward Insights. "The real estate stays the same, but you can keep adding levels. And, by adding levels, you can reduce the cost per bit because there are more memory cells, but the real estate to store them does not increase."
With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve. As the process becomes smaller and smaller in planar NAND flash technology, electrons more and more often leak through thinner cell walls creating data errors, requiring ever increasingly sophisticated error correction code.
Sign up for CIO Asia eNewsletters.