Samsung Electronics announced today that it has begun mass producing a 128-gigabit (Gb), 3-bit multi-level-cell (MLC) NAND memory chip using sub-20 nanometer (nm)-class process technology.
The flash chip will be used to create Samsung's highest-density, single-layer memory for use in embedded NAND storage and solid state drives (SSDs).
Today, flash vendors are beginning to experiment with 3D or multi-layer flash for even denser products.
Most NAND flash today stores up to two bits of data per cell. Single-level cell (SLC) flash, which natively has higher endurance and performance than MLC flash, is more costly as it does not store data as densely. It's typically reserved for higher-end flash products.
The new flash chips will be used in SSDs for notebooks PCs, desktop PCs and servers, and as storage in next-generation mobile devices, such as smartphones and tablets that require high densities, said Kathy Choe Thomas, a senior manager for NAND product marketing at Samsung Semiconductor.
Three-bit per cell NAND technology, sometimes referred to as triple-level cell (TLC) flash, requires greater error correction code (ECC) as the more data that is stored per cell, the more likely it is to leak through to other cells and cause data errors.
Thomas said Samsung's NAND controller can "easily manage" any added ECC requirements of the TLC flash.
"The new chip is a critical product in the evolution of NAND flash, one whose timely production will enable us to increase our competitiveness in the high density memory storage market," Young-Hyun Jun, executive vice president for Samsung's memory sales & marketing, said in a statement.
Samsung claims its 128Gb NAND flash chips have the industry's highest density as well as the highest performance level of 400Mbps data transfer rate based on the toggle DDR 2.0 interface. While Samsung said the new memory is produced using its densest lithography process - between 10 and 20nm - it would not say exactly what the size of the circuitry is.
And, Samsung is not alone in producing 3-bit per cell, sub-20nm NAND flash. SanDisk and Toshiba jointly developed and have been using 19nm lithography process to create NAND flash with 3 bits per cell since last year.
Joseph Unsworth, vice president of Gartner's NAND flash & SSD resarch, said Samsung has been performing very well in the NAND market due to their diversity in end-customers and leadership on 3-bits per cell flash technology. he said the news of this latest mass production "is an extension of that."
"The key is when will they get this designed into embedded and SSD markets," Unsworth said.
The 128Gb NAND flash chips will be used by Samsung in its 128Gbyte (GB) memory cards. Samsung said it will now also increase its production volume of SSDs with densities over 500GB capacity for wider adoption of SSDs in computer systems, "while leading the transition of main storage drives in the notebook market from hard disk drives (HDDs) to SSDs."
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