Subscribe / Unsubscribe Enewsletters | Login | Register

Pencil Banner

Intel rushes to exascale with redesigned supercomputing chip

Agam Shah | Nov. 20, 2013
Intel promises big performance and power improvements with the redesigned Xeon Phi chip, code-named Knights Landing.

As supercomputing speeds increase, the integration of a CPU and accelerator will provide highly parallel applications with more internal bandwidth, said Patrick Moorhead, president and principal analyst at Moor Insights and Strategy.

"With Knights Landing as a host CPU, Intel hopes to serve those massively parallel workloads that need minimal latency that comes with today's accelerators that use the PCI-Express bus," Moorhead said.

Real World Tech analyst David Kanter said the chip could have many embedded DRAM units, as in the company's recent chips code-named Haswell. Additionally, lots of larger-capacity DRAM could dot the chip, much like memory on graphics cards.

Many companies are heading in the direction of stacking chips -- also called 3D structuring -- on top of each other to save space and improve throughput. But the memory units in Knights Landing may not be stacked as it could be expensive and cause more leakage, Kanter said.

"Stacking memory on top makes sense, but if you have a 200- to 300-watt chip under it, doesn't make sense," Kanter said.

A big improvement on Knights Landing is support for single-threaded applications, Kanter said. Accelerator chips today focus mostly on highly parallel applications, leaving single threaded applications hanging to be processed by other hardware units. Such computing can be inefficient, Kanter said.

Also, developers won't have to worry about writing code in which processing is redirected to different hardware, analysts said.

Knights Landing will be made using the 14-nanometer manufacturing process. The first 14-nm chips are expected to reach PCs in the second half of this year, and Knights Landing could follow.

 

 

Previous Page  1  2 

Sign up for CIO Asia eNewsletters.