Credit: flickr/Goeff Hutchison
The interplay of size and time may make carbon nanotubes the answer to the computer industry's prayers as it grapples with pressure to make silicon chips ever-smaller. Or the same factors may turn CNTs into a technological dead end.
Size refers to the dimensions of carbon nanotubes (CNTs) vs. the shrinking geometry of the components on today's silicon chips. A CNT is basically a tube whose wall is 1 carbon atom thick. The tube itself is 1 nanometer (nm, or one billionths of a meter, or one-thousandths of a micron) in diameter, although it can be tens of microns long. Although made of carbon, single-wall CNTs are excellent conductors thanks to quantum conductance, which allows electrons to propagate along the length of the tubes.
Time refers to the progression of Moore's Law, an observation by Intel co-founder Gordon Moore that the number of components on a chip can be expected to double every two years, without an increase in price. According to that, about more eight years from now silicon technology, which has reached 14nm geometry, will reach the atomic level. At that time, presumably the industry will no longer be able to uphold Moore's Law by making silicon components continually smaller.
Will CNTs, with their 1nm geometry, be ready by then?
"We feel that CNTs have a chance to possibly replace silicon transistors sometime in the future -- if critical problems are solved," says Supratik Guha, director of physical sciences at IBM Research.
"I am hopeful that CNTs will be used one day," says Max Shulaker, a Stanford graduate student who serves as its spokesman for CNT research.
Tiny roadblocks with huge impacts
The problem of laying down chip circuits with CNTs that match the size of silicon components hasn't been solved, Guha notes. Since individual CNTs don't carry enough current for a functional transistor, five or six parallel tubes are required for one connection. The tubes must be laid 6nm or 7nm apart to minimize interference, but greater separation would waste space.
"Currently we are able to space them 100nm apart, so an order of magnitude improvement is needed," Guha says. "This is where we need some new thinking. With the current separation there is no advantage over silicon."
A silicon circuit that's more than 30nm wide isn't an issue, as metal traces in 14nm devices are about 50nm wide, notes semiconductor industry analyst Linley Gwennap, head of The Linley Group. "There is nothing in a 14nm process that actually measures 14nm," he says, adding that the fin, or main body, of an Intel transistor at the 14nm level measures 10nm.
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