More than seven years in the making, AMD on Tuesday unveiled what it believes will be a game-changing technology: a superfast, stacked chip technology called High Bandwidth Memory. Even better, the company crowed: Nvidia is at least a year behind it.
Using stacked RAM chips that communicate through tiny holes, High Bandwidth Memory offers three times the performance of traditional GDDR5 that's used by GPUs today and drastically reduces power consumption too, said AMD Chief Technology Officer Joe Macri, who oversaw HBM's development.
Why this matters: A graphics card's memory bandwidth matters as much to game performance as the graphics processor. An increase in memory bandwidth almost always means more performance, too, when coupled with changes to the GPU.
Modern graphics cards drink memory bandwidth like a big-block V8 drinks gas. The problem is the current memory, GDDR5, is rapidly approaching the point of diminishing returns, Macri said. To add more memory bandwidth using GDDR5 would consume too much power to be an effective performance boost.
Part of GDDR5's problem is how the chips connect to the GPU. GDDR5 RAM uses contacts at the edges of the individual chips. To add more bandwidth, you add more chips. But those chips must be laid out on a videocard's circuit board alongside each other, which leads to a suburban sprawl-like issue. Besides consuming a lot of space on the printed circuit board, it also means very long wires or traces must be run to reach the GPU. And it's not just the RAM chips--the power plants or voltage regulators to run that suburban sprawl also have to be factored in. Because you're pushing more signals along longer wires, you have to use more power, which means larger voltage regulators.
HBM addresses the limitations of GDDR5 by going vertical like a high-rise. By stacking four memory chips, AMD can get the RAM closer to the GPU, which shortens the wire length drastically. Unlike GDDR5, HBM RAM uses a technique called through-silicon vias or TSVs, that string wires vertically through holes in a stack of chips. Each layer also connects to the next directly using tiny bump contacts.
Because the layers interconnect and the wires don't have to go as far to reach the GPU, it's possible to make the bus far wider without incurring the power consumption of GDDR.
The dividends, Macri said, are radical. A GDDR5 chip, today, for example will support a 32-bit-wide memory bus with up to 7GBps of bandwidth. A single stack of HBM RAM supports a 1,024-bit-wide bus and more than 125GBps of memory bandwidth. That HBM chip also runs at a far lower clock speed while achieving a magnitude more memory bandwidth.
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