Subscribe / Unsubscribe Enewsletters | Login | Register

Pencil Banner

WD preparing to ship flash chips with half a terabit of capacity

Lucas Mearian | July 27, 2016
The new chips increase density by 33%

Western Digital (WD) has begun manufacturing the third generation of its 3D NAND flash chips, which increases the number of layers from 48 to 64 and will allow it to double capacity.

Pilot production of the new 64-layer chips has already started in WD's Yokkaichi, Japan joint venture fabrication plant; initial shipments are expected in the fourth quarter of this year with "meaningful commercial volumes" beginning in the first half of 2017.

screen shot 2015 08 04 at 5.10.00 pm

Toshiba's 48-layer 3D NAND chips.

In 2015, SanDisk and its technology partner Toshiba announced it was manufacturing the world's first 48-layer 3D NAND product using BiCS (Bit-Cost Scalable NAND) technology. That BiCS NAND flash chip offered 256Gbit (32GB) of capacity and stored 3-bit-per-cell (transistor). The latest iteration of the technology is called BiCS3.

BiCS 3D NAND Toshiba 

SanDisk and Toshiba announced last year they are manufacturing 256Gbit (32GB), 3-bit-per-cell (X3) 48-layer 3D NAND flash chips that offer twice the capacity of the next densest memory. The 3D NAND technology is called BiCS, short for Bit Cost Scaling.

In March, SanDisk shareholders approved a $19 billion buyout by Western Digital.

BiCS3, which is still jointly being developed with manufacturing partner Toshiba, will be initially deployed in 256Gbit capacities. But it will be available in a range of capacities up to half a terabit on a single chip.

Unlike 2D or planar NAND, which consists of a flat layer of NAND flash cells, 3D NAND stacks the cells vertically like a skyscraper.

sandisk 3d nand slide

As 2D NAND approaches scaling limits due to lithography size and error rates, layer stacking to produce 3D NAND obviates those concerns. This image shows horizontally stacked conductive polysilicon layers around a central memory hole that provide the stacked NAND bits. The circular hole minimizes neighboring bit disturb and allows overall density to rise.

"The launch of the next generation 3D NAND technology based on our industry-leading 64-layer architecture reinforces our leadership in NAND flash technology," Siva Sivaram, executive vice president of WD memory technology, said in a statement. "BiCS3 will feature the use of 3-bits-per-cell technology along with advances in high aspect ratio semiconductor processing to deliver higher capacity, superior performance and reliability at an attractive cost."

WD is not alone in its development of 3D NAND. In 2013, Samsung became the first to introduce a vertical TLC "V-NAND," a 32-layer cell structure based on Charge Trap Flash (CTF) and vertical interconnect process technology to link the cell array.


1  2  Next Page 

Sign up for CIO Asia eNewsletters.