But along with more cores came the challenge of making programs work in parallel. Programming frameworks like OpenCL, which is supported by Epiphany V, have helped write code that harnesses the joint computing power of many cores.
The Epiphany V design makes it easy to run applications in parallel. It has a mesh topology, and cores are networked to facilitate communications.
It has shared memory accessible to all cores. The topography ensures there is cache coherency, which is important in chips loaded with cores and memory. The shared memory support can expand to more Epiphany chips.
The mesh topology, with cores communicating via mini-routers, has been used in research and commercial chips before, but Epiphany V has a different design.
Some key details, like overall power consumption, aren't yet known. The power efficiency of the chips determines motherboard and server design, and also the effective performance per watt of the chip. For example, the 1,000-core KiloCore is so power-efficient that it can run on a single AA battery, the UC Davis researchers claimed.
Adapteva has released Epiphany chips previously, and also shipped the US $99 Parallella board computer with a previous Epiphany chip. The company turned to Kickstarter for funding to develop the board and shipped more than 10,000 units. Olofsson didn't detail how he'd commercialize the new Epiphany V chip.
Sign up for CIO Asia eNewsletters.