Subscribe / Unsubscribe Enewsletters | Login | Register

Pencil Banner

Bit by bit, Intel looks to quadruple SSD storage

Agam Shah | March 31, 2015
Intel is looking to cram four bits per cell in an effort to cram more storage into SSDs.

Each time one more bit is added to a cell, there is more interference, which could make it harder to discern data from a cell.

"The expectation for digital data is that it's 100 percent there or useless," Handy said.

Moreover, this isn't the first time a company has tried to cram four bits in a cell. M-Systems tried the same close to a decade ago, but failed. SanDisk ultimately acquired M-Systems in 2006.

Additionally, there isn't much incentive to put four bits per cell because of cost issues. It's possible to cut the cost of a flash chip in half by putting two bits in a cell, and by 30 percent by putting three bits in a cell. The savings could diminish to 15 percent when putting four bits per cell, according to Handy's estimates.

But Intel's Leszinske remained cautiously optimistic about the company's chances with QLC, saying Intel's 3D NAND technology has high capacitance and low interference, making quad-level cell "a real opportunity."

 

Previous Page  1  2 

Sign up for CIO Asia eNewsletters.